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search query: @instructor Roos, Janne / total: 7

references: 1-7 / 7

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	title	year	author
1.	Partitioning and macromodel-based model-order reduction for RLC circuits	2010	Miettinen, Pekka
2.	Efficient Time-Domain Simulation of Interconnects Characterized by Large RLC Circuits or Tabulated S Parameters	2004	Palenius, Timo
3.	Order Reduction of Interconnect Circuits	2003	Aaltonen, Sakari
4.	Generation of simulation models from measurement data using interpolation and radial basis function networks	2003	Pohjala, Anna
5.	Time-domain simulation of reduced-order interconnect models	2002	Palenius, Timo
6.	Parallel Hierarchical DC Analysis	2002	Honkala, Mikko
7.	Improving speed and convergence of APLAC's DC analysis	1999	Honkala, Mikko

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