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Author: | Chi, Huageng |
Title: | Hardware Design of Decoder for Low-Density Parity Check Codes |
Publication type: | Master's thesis |
Publication year: | 2009 |
Pages: | x + 62 Language: eng |
Department/School: | Elektroniikan, tietoliikenteen ja automaation tiedekunta |
Degree programme: | Elektroniikan ja sähkötekniikan tutkinto-ohjelma |
Main subject: | Tietoliikennetekniikka (S-72) |
Supervisor: | Östergård, Patric |
Instructor: | Rautio, Mika |
Electronic version URL: | http://urn.fi/URN:NBN:fi:aalto-201203071302 |
OEVS: | Electronic archive copy is available via Aalto Thesis Database.
Instructions Reading digital theses in the closed network of the Aalto University Harald Herlin Learning CentreIn the closed network of Learning Centre you can read digital and digitized theses not available in the open network. The Learning Centre contact details and opening hours: https://learningcentre.aalto.fi/en/harald-herlin-learning-centre/ You can read theses on the Learning Centre customer computers, which are available on all floors.
Logging on to the customer computers
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Location: | P1 Ark S80 | Archive |
Keywords: | low-density parity check (LDPC) decoder FPGA multi-rate multi-length layered decoding out-of-order memory-write multi-size shifter |
Abstract (eng): | A hardware decoder architecture is presented in this thesis for quasi-cyclic (QC) low-density parity check (LDPC) codes. The decoder is real-time configurable and supports 15 codes which are combination of 3 rates and 5 lengths. The partly parallel architecture implements layered decoding. A check node decoder is serial and implements min-sum correction algorithm. The proposed design techniques include out-of-order memory-write, two-stage multi-size shifter, serial decoding termination. The decoder consumes about half amount of logic resource on the Xilinx FPGA chip XC2VP50-5F1152. The worst case throughput at 20 iterations ranges from 5 Mbits to 60 Mbits (information bits) per second. Higher throughput can be obtained by the proposed optimisation. Reuse for similar codes is possible. |
ED: | 2009-10-06 |
INSSI record number: 38425
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