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Author:Korpinen, Pekka
Title:Using reconfigurable hardware to distribute network traffic for parallel processing
Verkkoliikenteen hajauttaminen rinnakkaisprosessoitavaksi ohjelmoitavan piirin avulla
Publication type:Licentiate thesis
Publication year:2009
Pages:95      Language:   eng
Department/School:Signaalinkäsittelyn ja akustiikan laitos
Main subject:Signaalinkäsittelytekniikka   (S-88)
Supervisor:Skyttä, Jorma
Instructor:Luoma, Marko
Electronic version URL: http://urn.fi/urn:nbn:fi:tkk-S100045
OEVS:
Electronic archive copy is available via Aalto Thesis Database.
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Reading digital theses in the closed network of the Aalto University Harald Herlin Learning Centre

In the closed network of Learning Centre you can read digital and digitized theses not available in the open network.

The Learning Centre contact details and opening hours: https://learningcentre.aalto.fi/en/harald-herlin-learning-centre/

You can read theses on the Learning Centre customer computers, which are available on all floors.

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Opening a thesis

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    Aalto Thesis Database

  • Click on the icon to search for and open the thesis you are looking for from Aaltodoc database. You can find the thesis file by clicking the link on the OEV or OEVS field.

Reading the thesis

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Printing the thesis

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Location:P1 Ark S80     | Archive
Keywords:hardware design
reconfigurable hardware
FPGA
Ethernet
network processing
distributed computing
laitteistosuunnittelu
ohjelmoitavat piirit
FPGA
Ethernet
verkkoliikenteen prosessointi
hajautettu laskenta
Abstract (eng): The expanding diversity and amount of traffic in the Internet requires increasingly higher performing devices for protecting our networks against malicious activities.
The computational load of these devices may be divided over multiple processing nodes operating in parallel to reduce the computation load of a single node.
However, this requires a dedicated controller that can distribute the traffic to and from the nodes at wire-speed.
This thesis concentrates on the system topologies and on the implementation aspects of the controller.

A field-programmable gate array (FPGA) device, based on a reconfigurable logic array, is used for implementation because of its integrated circuit like performance and high-grain programmability.
Two hardware implementations were developed; a straightforward design for 1-gigabit Ethernet, and a modular, highly parameterizable design for 10-gigabit Ethernet.
The designs were verified by simulations and synthesizable test benches.
The designs were synthesized on different FPGA devices while varying parameters to analyze the achieved performance.
High-end FPGA devices, such as Altera Stratix family, met the target processing speed of 10-gigabit Ethernet.
The measurements show that the controller's latency is comparable to a typical switch.
The results confirm that reconfigurable hardware is the proper platform for low-level network processing where the performance is prioritized over other features.
The designed architecture is versatile and adaptable to applications expecting similar characteristics.
Abstract (fin): Internetin edelleen lisääntyvä ja monipuolistuva liikenne vaatii entistä tehokkaampia laitteita suojaamaan tietoliikenneverkkoja tunkeutumisia vastaan.
Tietoliikennelaitteiden kuormaa voidaan jakaa rinnakkaisille yksiköille, jolloin yksittäisen laitteen kuorma pienenee.
Tämä kuitenkin vaatii erityisen kontrolloijan, joka kykenee hajauttamaan liikennettä yksiköille linjanopeudella.
Tämä tutkimus keskittyy em. kontrolloijan järjestelmätopologioiden tutkimiseen sekä kontrolloijan toteuttamiseen ohjelmoitavalla piirillä, kuten kenttäohjelmoitava järjestelmäpiiri (eng. field programmable gate-array, FPGA).
Kontrolloijasta tehtiin yksinkertainen toteutus 1-gigabitin Ethernet-verkkoihin sekä modulaarinen ja parametrisoitu toteutus 10-gigabitin Ethernet-verkkoihin.
Toteutukset verifioitiin simuloimalla sekä käyttämällä syntetisoituvia testirakenteita.
Toteutukset syntetisoitiin eri FPGA-piireille vaihtelemalla samalla myös toteutuksen parametrejä.
Tehokkaimmat FPGA-piirit, kuten Altera Stratix -piirit, saavuttivat 10-gigabitin prosessointivaatimukset.
Mittaustulokset osoittavat, että kontrollerin vasteaika ei poikkea tavallisesta verkkokytkimestä.
Työn tulokset vahvistavat käsitystä, että ohjelmoitavat piirit soveltuvat hyvin verkkoliikenteen matalantason prosessointiin, missä vaaditaan ensisijaisesti suorituskykyä.
Suunniteltu arkkitehtuuri on monipuolinen ja soveltuu joustavuutensa ansiosta muihin samantyyppiseen sovelluksiin.
ED:2009-06-15
INSSI record number: 37685
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