search query: @keyword matala käyttöjännite / total: 7
reference: 3 / 7
Author: | Routama, Jarkko |
Title: | An integrated low voltage 150Mbit/s cable communication circuit and a CMOS clock recovery phase and frequency locked loop |
Integroitu matalan käyttöjännitteen 150Mbit/s tiedonsiirtopiiri ja CMOS vaihe- ja taajuuslukittu lukko datan uudelleenajastukseen | |
Publication type: | Licentiate thesis |
Publication year: | 1998 |
Pages: | 58 Language: eng |
Department/School: | Sähkö- ja tietoliikennetekniikan osasto |
Main subject: | Piiritekniikka (S-87) |
Supervisor: | Halonen, Kari |
Instructor: | Koli, Kimmo |
OEVS: | Electronic archive copy is available via Aalto Thesis Database.
Instructions Reading digital theses in the closed network of the Aalto University Harald Herlin Learning CentreIn the closed network of Learning Centre you can read digital and digitized theses not available in the open network. The Learning Centre contact details and opening hours: https://learningcentre.aalto.fi/en/harald-herlin-learning-centre/ You can read theses on the Learning Centre customer computers, which are available on all floors.
Logging on to the customer computers
Opening a thesis
Reading the thesis
Printing the thesis
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Location: | P1 Ark S80 | Archive |
Keywords: | Jitter PLL dead zone equalizer process and temperature variations low voltage Jitteri kuollut alue korjain prosessi ja lämpötila hajonnat matala käyttöjännite |
ED: | 1998-12-31 |
INSSI record number: 13792
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