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Author: | Palenius, Timo |
Title: | Efficient Time-Domain Simulation of Interconnects Characterized by Large RLC Circuits or Tabulated S Parameters |
Suurien RLC-piirien tai taulukoitujen S-parametrien avulla kuvattujen piirikytkentöjen tehokas aika-alueen simulointi | |
Publication type: | Licentiate thesis |
Publication year: | 2004 |
Pages: | 92 Language: eng |
Department/School: | Sähkö- ja tietoliikennetekniikan osasto |
Main subject: | Teoreettinen sähkötekniikka (S-55) |
Supervisor: | Valtonen, Martti |
Instructor: | Roos, Janne |
OEVS: | Electronic archive copy is available via Aalto Thesis Database.
Instructions Reading digital theses in the closed network of the Aalto University Harald Herlin Learning CentreIn the closed network of Learning Centre you can read digital and digitized theses not available in the open network. The Learning Centre contact details and opening hours: https://learningcentre.aalto.fi/en/harald-herlin-learning-centre/ You can read theses on the Learning Centre customer computers, which are available on all floors.
Logging on to the customer computers
Opening a thesis
Reading the thesis
Printing the thesis
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Location: | P1 Ark S80 | Archive |
Keywords: | circuit simulation interconnect simulation model-order reduction frequency-domain model transient analysis APLAC piirisimulointi interconnect-simulointi malliredusointi taajuusalueen malli transienttianalyysi APLAC |
ED: | 2005-01-17 |
INSSI record number: 26646
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