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Author:Ylivaara, Oili
Title:NMOS prosessin viivanleveyden kavennuksen evaluointi RF-sovelluksiin
Evaluation of NMOS process linewidth decrease for RF Applications
Publication type:Master's thesis
Publication year:2005
Pages:ix + 56 s. + liitt. 12      Language:   fin
Department/School:Materiaalitekniikan osasto
Main subject:Metalli- ja materiaalioppi   (Mak-45)
Supervisor:Lehto, Ari
Instructor:Ronkainen, Hannu
OEVS:
Electronic archive copy is available via Aalto Thesis Database.
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Location:P1 Ark V80     | Archive
Keywords:gate linewidth
polycrystalline silicon
i-line photoresist
spacer process
NMOS
viivanleveys
monikiteinen pii
i-viivan fotoresisti
spacer-prosessi
Abstract (eng): In this work critical process steps for NMOS transistor gate line width decrease are studied.
These are the uniformity of etching process of the gate, lithography steps and spacer processing.
These individual process steps were optimised for 0.6 -micrometer line width and the results were used for processing the NMOS transistors.
The NMOS process was carried out with line widths of 1.0 and 1.2 micrometers.

The results from critical process stages optimised for 0.6 -micrometer line width shows reproducible results.
Measurement results from 1.0 and 1.2 µm transistor show that the process that was optimised for 0.6 -micrometer line widths implemented to NMOS process lead to functional components.
By using the mask set designed for 0.6 -micrometer line widths it is possible to process 0.6 -micrometer devices.
Abstract (fin): Tässä työssä käsitellään NMOS-prosessin kannalta kriittisiä prosessivaiheita pyrittäessä kohti kapeampaa viivanleveyttä transistorin hilassa.
Erityisesti huomioitavia prosessivaiheita ovat hilan etsausprosessin tasaisuus, litografia vaiheet Ja spacer-prosessi.
Nämä yksittäiset prosessivaiheet optimoitiin 0,6 mikrometrin viivanleveydelle ja tuloksia käytettiin hyväksi prosessoitaessa NMOS 1,2 ja 1,0 mikrometrin viivanleveyksille.

Valmiista rakenteista mitatut tulokset vahvistavat, että prosessivaiheiden optimointi 0,6 mikrometrin viivanleveydelle on mahdollista.
Prosessilla tuotetut toimivat 1,2 ja 1,0 µm transistorit todistavat, että karakterisoidut kriittiset prosessivaiheet yhdistettyinä NMOS-prosessiin tuottavat toimivia komponentteja halutuilla parametreillä.
Suunnittelemalla käytetyt maskisarjat 0,6 mikrometrin viivanleveydelle on mahdollista tuottaa 0,6 mikrometrin komponentteja.
ED:2005-04-04
INSSI record number: 28249
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