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Author:Rodriguez Ramos, Alejandro
Title:Low-power and high-fanout bus design techniques
Publication type:Final Project work
Publication year:2014
Pages:vii + 49 s. + liitt. 17      Language:   eng
Department/School:Mikro- ja nanotekniikan laitos
Main subject:Mikro- ja nanotekniikka   (S3010)
Supervisor:Ryynänen, Jussi
Instructor:Koskinen, Lauri
Electronic version URL: http://urn.fi/URN:NBN:fi:aalto-201407012290
OEVS:
Electronic archive copy is available via Aalto Thesis Database.
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Location:P1 Ark Aalto  1606   | Archive
Keywords:low-power
high-fanout
bus
hardware neural networks
network-on-chip
pulse width modulation
time-domain
pulse
width modulation
wire model
repeater
Abstract (eng):Low-power techniques pose an important concern, when designing autonomous electronic devices.
Most of the upcoming applications increasingly demand high performance and low-power consumption.
In this thesis work, two low-power and high-fanout bus design techniques are reviewed.
Pulse Width Modulation (PWM) and Time-Domain Conversion (TDC) approaches are elucidated.
Schematic simulations (Cadence), quantitative and comparative results of both approaches are included.
Additionally, on-chip wire theory is shown as well as some optimized bus simulation models (MATLAB), concluding with a summary of the main application areas for this techniques.
Finally , two ready-to-use library cells are generated, as well as Verilog code for the TDC system.
ED:2014-08-03
INSSI record number: 49380
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